File:Cmos-chip structure in 2000s (en).svg
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Summary
DescriptionCmos-chip structure in 2000s (en).svg |
Català: Estructura esquemàtica d'un xip CMOS, tal com es va construir a principis dels anys 2000. El gràfic mostra els LDD-MISFET sobre un substrat de silici SOI amb cinc capes de metal·lització i un tap de soldadura per a la unió de xip. També mostra la secció per a FEOL (front-end de línia), BEOL (back-end de línia) i les primeres parts del procés de back-end. (versió traduïda a l'alemany)
English: Schematic structure of a CMOS chip, like it is built in the early 2000s. The graphic shows LDD-MISFET's on a SOI silicon substrate with five metallization layers and solder bump for flip-chip bonding. Also it shows the section for FEOL (front-end of line), BEOL (back-end of line) and first parts of back-end process. (translated German version) |
Date | 9 December 2006 (upload date) |
Source | self made (from university scripts and scientific papers) |
Author | Cepheiden |
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Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.2 or any later version published by the Free Software Foundation; with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A copy of the license is included in the section entitled GNU Free Documentation License.http://www.gnu.org/copyleft/fdl.htmlGFDLGNU Free Documentation Licensetruetrue |
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9 December 2006
image/svg+xml
98b4a7c115393efaade08e41f7203a44dae22f52
140,823 byte
810 pixel
550 pixel
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Date/Time | Dimensions | User | Comment | |
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current | 07:35, 5 February 2024 | 550 × 810 (138 KB) | Manlleus | File uploaded using svgtranslate tool (https://svgtranslate.toolforge.org/). Added translation for ca. |
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Width | 550 |
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Height | 810 |